This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-130969, filed Apr. 27, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to a pattern formation method, a mask for exposure used for pattern formation, and a method of manufacturing the same, and more specifically to a mask for exposure used in the manufacture of a semiconductor device such as an IC or an LSI, a method of manufacturing the mask for exposure, and a pattern formation method using the mask for exposure.
2. Description of the Related Art
In recent years, semiconductor manufacturing techniques have made remarkable progress. At present, volume production of a semiconductor chip having a pattern size in which the minimum processing size is 0.18 xcexcm has commenced. Such a scaled-down semiconductor device has been made possible due to quantum leaps in micropattern forming techniques. Examples of micropattern forming techniques are mask processes, optical lithography, and etching.
In the era of sufficiently large pattern sizes, a device pattern substantially the same as a design pattern could be formed. For example, if the size of a semiconductor device to be manufactured is sufficiently large, the device pattern thereof is drawn on a mask substrate as a design pattern. Then a mask pattern (mask for exposure) the same as the design pattern is formed. The mask pattern is transferred onto a wafer, on which a underlying layer is formed, by an optical projection system. The underlying layer is etched in accordance with the resist pattern thus formed. Thereby, device patterns having substantially the same pattern size as that of the design pattern can be formed on the wafer.
However, the accuracy of the pattern formation in each process has deteriorated in parallel with advances in scaling-down semiconductor devices. This causes a problem that the resultant size (pattern size) on the wafer does not coincide with that of the design pattern. In the processes of lithography and etching especially, the layout environment of the peripheral portion of a pattern to be formed (peripheral pattern environment) greatly influences the accuracy of the resultant pattern size. As a method of reducing such influences, correction techniques such as OPC (Optical Proximity Correction) or PPC (Process Proximity Correction) are already known. The optical proximity correction technique is a technique of adding, in advance, an auxiliary pattern to a design pattern, so that the resultant pattern after being processed is formed in a desired size (refer, for example, to Jpn. Pat. Appln. KOKAI Publication No. 9-319067).
Also in recent years, a technique called xe2x80x9cresolution enhancement technique (RET)xe2x80x9d has become indispensable. With the RET, a lithography process margin can be improved in forming a pattern such as a memory cell having a plurality of fine patterns densely packed. On the other hand, however, the influence of OPE (Optical Proximity Effects) becomes considerably larger than when not using RET. More specifically, it is assumed that a high-density portion and a low-density portion are exposed with an exposure dose by using a mask pattern of the same size. In such a case, a desired size pattern can be obtained in the high-density portion. On the other hand, in the low-density portion, the size may be smaller or larger than a desired size.
For example, in the case of a memory cell, the layout (density) of the cell pattern (device pattern) considerably varies between the central portion of the cell and the end portion thereof (hereinafter referred to as xe2x80x9ccell endxe2x80x9d). Thus, collapse of a resist pattern occurs in the cell end (low-density portion in this case) because of the large OPE. In order to avoid this problem, in general, a method of disposing a predetermined number of extra dummy patterns in the endmost portion of the cell (further outside of the cell end) is adopted (refer, for example, to Jpn. Pat. Appln. KOKAI Publication No. 2-177558). Alternatively, only the size of the resist pattern in the cell end is made larger (or smaller) than that of the central portion of the cell. Thereby, collapse of the resist pattern in the cell end is avoided.
However, if dummy patterns are disposed, the area of a cell increases, which causes upsizing of a chip and leads to reduction in competitiveness in manufacturing of a semiconductor device. Further, even if only the size of the mask pattern at the cell endmost is varied, a finished size on the wafer at/near the cell end changes because the optical proximity effects depend on the peripheral pattern environment of about 5 xcexcm at maximum (generally, 2 to 3 xcexcm). Consequently, it""s difficult to obtain sufficient cell/device characteristics.
According to a first aspect of the present invention, there is provided a pattern formation method comprising: separating a memory cell pattern of each of a plurality of memory cells into a first pattern group provided at a predetermined position inside from an endmost portion of a cell and a second pattern group excluding the first pattern group;
determining a mask size of the second pattern group such that the second pattern group secures a sufficient process margin relative to a given size and size accuracy;
optimizing a mask size of the first pattern group according to a peripheral pattern environment such that the first pattern group has a desired size under a condition for determining the mask size of the second pattern group;
forming a mask pattern of the memory cell according to the mask size of the second pattern group determined and the mask size of the first pattern group optimized; and
forming the cell pattern on a semiconductor wafer, using the mask pattern.
According to a second aspect of the present invention, there is provided a method of manufacturing a mask for exposure comprising:
separating a memory cell pattern of each of a plurality of memory cells into a first pattern group provided at a predetermined position inside from an endmost portion of a cell and a second pattern group excluding the first pattern group;
determining a mask size of the second pattern group such that the second pattern group secures a sufficient process margin relative to a given size and size accuracy;
optimizing a mask size of the first pattern group according to a peripheral pattern environment such that the first pattern group has a desired size under a condition for determined the mask size of the second pattern group; and
forming a mask pattern of the memory cell according to the mask size of the second pattern group determined and the mask size of the first pattern group optimized.
According to a third aspect of the present invention, there is provided a mask for exposure used when a memory cell pattern of a plurality of memory cells comprises a first pattern group provided at a predetermined position inside from an endmost portion of a cell, and a second pattern group excluding the first pattern group,
wherein the mask for exposure comprises a mask pattern of the memory cell formed according to a mask size of the first pattern group and a mask size of the second pattern group,
the mask size of the second patter group which forms the mask pattern is determined by such a condition that the second pattern group secures a sufficient process margin relative to a given size and size accuracy, and
the mask size of the first pattern group which forms the mask pattern is optimized according to a peripheral pattern environment such that the first pattern group has a desired size under the condition.